1. Field of the Invention
This invention relates generally to the structure and fabrication process of planar DMOS power devices. More particularly, this invention relates to a novel and improved DMOS device structure and fabrication process. Specially configured body mask is employed to laterally shift the body regions such that the body regions are spaced farther away from each other. The size of the DMOS can be reduced by reducing the gate-width without unduly increasing the JFET resistance. This is achieved by maintaining substantially a constant distance between the body regions when the gate-width is reduced. Furthermore, specially configured gapped-gates are formed to reduce the gate capacitance such that the speed of the MOSFET device is increased. Simplified manufacture processes are applied to maintain a low production cost and to improve the device reliability.
2. Description of the Prior Art
Conventional structure and processing steps for fabricating a power metal oxide silicon field effect transistor (MOSFET) power device are limited by several technical difficulties. Specifically, conventional planar cellular structure of power MOSFETs, such as square, circular, and hexagonal topologies are limited by the difficulty that the on-resistance is decreased when the polysilicon space is reduced to achieve higher cell density by shrinking unit cell areas. However, the surface area occupied by the polysilicon gate electrode limits a further increase of cell density for the planar DMOS. Additional reduction in the size of the gate electrode exacerbates the parasitic JFET pinching effect, leading to higher device on-resistance at a small cell pitch. Conversely, if the polysilicon gate dimension is held constant to avoid the pinching effect, and the size of the source/body region, i.e., the opening in the polysilicon, is reduced instead, the specific on-resistance still increases at high cell densities. This is caused by the transistor gate width per unit area decreases. With such electrical and geometric restrictions, the cell density is limited to 6.5 million cells/inch.sup.2. For a person of ordinary skill in the art, further increases in planar DMOS cell density is unwarranted and likely to be detrimental to performance. The pinching effect caused by cell pitch reduction has to be eliminated to significantly benefit power MOSFET specific on-resistance. Additionally, the JFET resistance can be reduced with a shallower body junction. However, the breakdown voltage of the device is degraded with shallower body junctions. The tradeoffs of these performance characteristics become designer's dilemmas, which cannot be easily resolved with conventional planar structures and current state of the art manufacturing technology.
FIG. 1 shows a typical vertical double diffused MOS (VDMOS) device which uses a double diffusion technique to control the channel length L. Two successive diffusions are performed with first a p diffusion using boron, then a n diffusion using either arsenic or phosphorus, to produce two closely spaced pn junctions at different depths below the silicon surface. With this pn-junction, as shown in FIG. 1, the VDMOS supports the drain voltage vertically in the N-epitaxial layer. The current flows laterally from the source through the channel parallel to the surface of the silicon. The current flow then turns through a right angle to flow vertically down through the drain epitaxial layer to the substrate and to the drain contact. The p-type "body" region in which the channel is formed when a sufficient positive voltage is applied, and the n+ source contact regions are diffused successively through the same window etched in the oxide layer. The channel length can be controlled through the processing steps. Because of the relative doping concentrations in the diffused.
As discussed above, when the width of the gates is reduced to increase the cell density, the body regions are pulled together. The JFET regions between the body regions are pinched and resulting in a higher JFET resistance, i.e., a higher R-JFET. Typically, for a body dopant such as boron, there is a ratio of lateral diffusion to vertical of approximately 0.8. Therefore, if the depth of the body is b, generally the body regions extend lateral from the edges of the gate with a distance of about 0.8b into a region under the gate. Referring to FIG. 1B, where a conventional MOSFET device is shown with the body regions formed by implanting the body dopant ions, which are blocked by the polysilicon gates. The body regions are then formed by carrying out a body diffusion. The body regions as shown have a depth of b and a lateral diffusion length .lambda. of 0.8b measured from the edges of the gate. If the width of the gate is G, then the distance J between the body regions is approximately: EQU J=G-2.lambda.=G-2(0.8b)
As the width of the gate G is reduced, the distance J between the body regions is also reduced which causes the JFET resistance to increase. It appears, from Equation (1), that a longer distance of J may be maintained by keep a shallow P-body with reduced value of b. However, a shallow body would create several problems, e.g., device punch through, lower breakdown voltage and reduced device ruggedness. For these reasons, in a conventional MOSFET power device, it is difficult to maintain a same JFET resistance when the cell size is reduced.
In addition to above limitations, it is also difficult to improve the switching speed and meanwhile reducing the production cost of the DMOS power device. This is particularly true when the power DMOS devices become more complicate both in cell structure and in device topology. In the meantime, in order to achieve higher switching speed, it is desirable to reduce the gate-to-drain capacitance. However, a device structure capable of providing such performance improvement typically involves the application of more complex fabrication processes. As the fabrication processes become more complex and increased number of masks are required, longer manufacture time cycles become necessary, which leads to higher production costs. Complex fabrication processes with increased number of masks introduce further concerns. As more masks and processing steps are applied, more uncertainties of production yield and product reliability are introduced. The production costs are further impacted due to these undesirable factors. For these reasons, many technical improvements are attempted to improve the device performance to achieve higher switching speed while reducing the number of masks employed for MOSFET fabrication. Several MOSFET device structures and manufacture techniques are also disclosed in U.S. Patents.
In a U.S. Pat. No. 5,273,922, entitled "High Speed Low Gate/Drain Capacitance DMOS Device", (issued on Dec. 28, 1993), as that shown in FIG. 2, Tsoi discloses a DMOS device. Tsoi's device includes a field oxide in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implant impurity blow the field oxide reduce the on-resistance of the device. With these advantages achievable by Tsoi's DMOS device, it is however limited by a difficulty that the size of the transistors can not be further reduced to increase the cell density. The lateral dimension of a transistor cell is limited by a misalignment tolerance between the polysilicon gate and the field oxide. In order to avoid an increase in the device threshold.